[gmx-developers] Wallcycle bug?
Mark Abraham
mark.j.abraham at gmail.com
Tue Sep 15 23:43:13 CEST 2015
Sorry, https://gerrit.gromacs.org/#/c/5095/ is the relevant merge
Mark
On Tue, 15 Sep 2015 22:20 Szilárd Páll <pall.szilard at gmail.com> wrote:
> On Tue, Sep 15, 2015 at 10:11 PM, Mark Abraham <mark.j.abraham at gmail.com>
> wrote:
>
>> Hi,
>>
>> When verified, reviewed and merged, https://gerrit.gromacs.org/#/c/5094/ should
>> resolve this for master branch.
>>
>
> Are you referring to the TSC synchronization issue? The change you liked
> fixes #1823, a different issue.
>
> --
> Szilárd
>
>
>
>>
>> Mark
>>
>> On Tue, Sep 15, 2015 at 6:18 PM Szilárd Páll <pall.szilard at gmail.com>
>> wrote:
>>
>>> On Tue, Sep 15, 2015 at 5:16 PM, Berk Hess <hess at kth.se> wrote:
>>>
>>>> Hi,
>>>>
>>>> We didn't realize that modern x86 cpus no longer synchronize clocks
>>>> between cores.
>>>
>>>
>>> Actually, having read up a bit more, the _opposite_ seems to be the
>>> case: on older CPUs there could be a problem, but on newer ones the TSC
>>> should be:
>>> - "constant", i.e. not affected by frequency scaling,
>>> - "nonstop", i.e. unaffected by CPU ACPI states.
>>> The "constant_tsc" and "nonstop_tsc" cpuid flags indicate whether these
>>> are supported (most AMD and Nehalem+ on Intel).
>>>
>>> Intel seems to call both these cases "invariant TSC" (dev manual
>>> section 17.14.1 [1]). Apparently a number sources claim [2,3] that
>>> invariant TSC implies that TSC is synchronized (or can be if the BIOS
>>> syncs at boot) and the Intel docs seems to suggest this too by claiming
>>> that the OS can use TSC for wall clock.
>>>
>>>
>>> Based on this the issue you observed could only be caused by something
>>> funny with your BIOS (or OS/kernel?). Thoughts?
>>>
>>>
>>> Cheers,
>>> --
>>> Szilárd
>>>
>>>
>>> [1]
>>> http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf
>>>
>>> [2] http://www.gossamer-threads.com/lists/xen/devel/185419
>>>
>>> [3]
>>> https://software.intel.com/en-us/forums/intel-isa-extensions/topic/289368
>>>
>>> We should get the fix for this merged asap:
>>>> https://gerrit.gromacs.org/#/c/5091/
>>>>
>>>> Cheers,
>>>>
>>>> Berk
>>>>
>>>> On 09/15/2015 05:06 PM, David van der Spoel wrote:
>>>>
>>>>> Hi,
>>>>>
>>>>> my patch stumbled over this issue in Jenkins:
>>>>>
>>>>> Program: gmx mdrun, VERSION 5.2-dev-20150915-ef00eb4-local
>>>>> Source file: src/gromacs/timing/wallcycle.cpp (line 398)
>>>>> Function: void subtract_cycles(wallcc_t *, int, int)
>>>>>
>>>>> Assertion failed:
>>>>> Condition: wcc[ewc_main].c >= wcc[ewc_sub].c
>>>>> Subcounter cannot have more ticks than parent
>>>>>
>>>>> For more information and tips for troubleshooting, please check the
>>>>> GROMACS
>>>>> website at http://www.gromacs.org/Documentation/Errors
>>>>>
>>>>> Any clue? Or is this assertion just overly pedantic?
>>>>>
>>>>
>>>> --
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