[gmx-users] Pentium IV timings
E.Lindahl at chem.rug.nl
Thu Nov 1 16:30:17 CET 2001
Peter Tieleman wrote:
> Hi Erik,
> Does that mean you wrote SSE routines for PIV? Paul van Maaren replied to my
> question a while ago about PIVs saying it wasn't worth it because there are
> no assembly innerloops for PIVs. Probably an obvious question, but I'm due
> to spend the last of my equipment money within the next four months or so.
> Highest on the list is storage, plus a few nodes with myrinet. The nature of
> those nodes is still something I haven't decided, although dual athlons
> might be cool.
No, we don't have any SSE2 loops - but that would only be necessary for
double precision. In single precision you only use the normal SSE loops, and
they work just fine on P4's.
I would go for dual Athlons though - the Athlon MP is still reasonably priced
compared to the XP (non-SMP, even if the first ones could do SMP :-) while
intel has priced the SMP Xeon P4s completely out of range.
We're actually going with P3's when upgrading the cluster here. They are dirt
cheap even in SMP and they've been having so much possibly-heating-related
problems before that I didn't dare to recommend Athlons that get even hotter.
I might still write SSE2 loops just for double precision if people ask for it,
since the register is 128 bits wide we can only unroll things twice in double
precision, compared to a factor 4 in single. Double precision also requires
two Newton-Rhapson iterations instead of one, and we'll have to shuffle
twice as much memory. Thus, it would probably be much slower than the single
precision, so it might not be worth it.
And, since AMD will have a 64 bit processor that is backwards compatible
with IA32 intel just might have to reposition IA-64 as a consumer processor
much sooner than the'd prefer, so until McKinley is out and I've checked
the 2nd generation IA-64 assembly performance SSE2 will probably have to wait
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