[gmx-users] Re: Gromacs in Efficeion CPU's

Jorge Hernandez Fernandez jorgehf at cbi.cnptia.embrapa.br
Fri Oct 22 20:19:29 CEST 2004


Dear David:

 The Efficeion CPU has SSE and SSE2 support, and 1 MB L2 cache. The question 
is: Is any RPM for this CPU or we need to compile?

Thanks in advance:
                                    Jorge H.F.

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